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Low Power Single 2 Input Positive AND Gate,74AUP1G08XN5G Replace SN74AUP1G08
74AUP1G08XN5G 74AUP1G08XN5G.pdf
FEATURES

資料完善中

























PIN CONFIGUTION
優勢替代
SN74AUP1G08 SN74AUP1G08.pdf

No.13740

FEATURES

Available in the Ultra Small 0.64 mm2 Package

(DPW) With 0.5-mm Pitch

Low Static-Power Consumption:

ICC = 0.9 μA Maximum

Low Dynamic-Power Consumption:

Cpd = 4.3 pF Typical at 3.3 V

Low Input Capacitance: Ci = 1.5 pF Typical

Low Noise: Overshoot and 

  Undershoot<10% of VCC

Ioff Supports Live Insertion, Partial-

  Power-Down Mode, and Back Drive Protection

Schmitt-Trigger Action Allows Slow Input 

  Transition and Better Switching Noise 

  Immunity at the Input (Vhys = 250 mV Typical at 3.3 V)

Wide Operating VCC Range of 0.8 V to 3.6 V

Optimized for 3.3-V Operation

3.6-V I/O Tolerant to Support 

  Mixed-Mode Signal Operation

tpd = 4.3 ns Maximum at 3.3 V

Suitable for Point-to-Point Applications

Latch-Up Performance Exceeds 100 

  mA Per JESD 78, Class II

ESD Performance Tested Per JESD 22

  2000-V Human-Body Model(A114-B, Class II)

  1000-V Charged-Device Model (C101)

PIN CONFIGUTION
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